Metal-Oxide Semiconductor Field Effect Transistors (“MOSFETs”) are a common type of semiconductor device. A MOSFET device includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate structure adjacent to the channel region. The gate structure includes a conductive gate electrode layer adjacent to and separated from the channel region by a thin dielectric layer. When a voltage of sufficient strength is applied to the gate structure to place the MOSFET device in an on state, a conduction channel region forms between the source and drain regions thereby allowing current to flow through the device. When the voltage that is applied to the gate is not sufficient to cause channel formation, current does not flow and the MOSFET device is in an off state.
Three-dimensional (3D) integration of semiconductor chips typically employs through-substrate vias (TSVs) that connect the front side of a semiconductor chip to a back side of the same semiconductor chip. Multiple semiconductor chips may be vertically stacked employing the through-substrate vias (TSVs). Such three-dimensional integration of semiconductor chips provides a higher device density per area than a single semiconductor chip without any vertical stacking, and reduces the size of a packaging substrate correspondingly.
When MOSFETs are used in a 3D integration scheme, contact resistance may be important, depending on the application. Therefore, it is desirable to have a structure and method for forming a contact with reduced contact resistance that is compatible with a 3D integration scheme.